Propagating design tolerances to shape tolerances for lithography

ABSTRACT

An approach is provided that computes electrical delay ranges that correspond to a number of shapes included in a hardware design layout. The electrical delay ranges are converted to shape tolerances for each of the shapes. A lithography mask of the hardware design layout is generated using the shape tolerances so that the images of the shapes in the mask produced lie within the shape tolerances that correspond to the respective shape.

TECHNICAL FIELD

The present disclosure relates to an approach for understanding designtolerances in a semiconductor design. More specifically, the presentdisclosure relates to an approach that propagates these designtolerances to shape tolerances used in the lithographic process.

BACKGROUND

Lithography, such as photolithography, is a method used to structurematerial on a precise scale and is often used in the manufacture ofsemiconductors (e.g., microchips). Lithography employed to createsemiconductors uses a photomask as a master from which a final patternis created. Current methodologies of lithography treat the target layout(pattern) as a fixed requirement. Having fixed requirements inlithography is increasingly challenging due to modern semiconductordesigns that pack more and more design elements in a smaller package. Inorder to fit the increased number of design elements on a small package,tolerances of the mask must often be extremely tight. These tighttolerances result various challenges, such as increased time to create amask, which result in increased cost to manufacture the semiconductors.

SUMMARY

An approach is provided that computes electrical delay ranges thatcorrespond to a number of shapes included in a hardware design layout.The electrical delay ranges are converted to a shape tolerances for eachof the shapes. A lithography mask of the hardware design layout isgenerated using the shape tolerances so that the shapes in thelithography mask are masked within the shape tolerances that correspondto the respective shape.

The foregoing is a summary and thus contains, by necessity,simplifications, generalizations, and omissions of detail; consequently,those skilled in the art will appreciate that the summary isillustrative only and is not intended to be in any way limiting. Otheraspects, inventive features, and advantages of the present disclosure,as defined solely by the claims, will become apparent in thenon-limiting detailed description set forth below.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure may be better understood, and its numerousobjects, features, and advantages made apparent to those skilled in theart by referencing the accompanying drawings, wherein:

FIG. 1 is a block diagram example of a data processing system in whichthe methods described herein can be implemented;

FIG. 2 provides an extension example of the information handling systemenvironment shown in FIG. 1 to illustrate that the methods describedherein can be performed on a wide variety of information handlingsystems which operate in a networked environment;

FIG. 3 is a flow diagram showing the steps taken to generate shape slackinformation and lithography tolerance bands;

FIG. 4 is a flowchart showing the steps taken to pre-characterizelibrary cells that are stored in a shape library;

FIG. 5 is a flowchart showing the steps taken to convert electricalslack in the hardware design to physical shape slack;

FIG. 6 is a flowchart of a first phase in converting the electricalslack in the design to physical shape slack by analyzing the electricalslack distribution in the design; and

FIG. 7 is a flowchart of a second phase in converting the electricalslack in the design to physical shape slack by converting the delayslack to shape slack.

DETAILED DESCRIPTION

Certain specific details are set forth in the following description andfigures to provide a thorough understanding of various embodiments ofthe disclosure. Certain well-known details often associated withcomputing and software technology are not set forth in the followingdisclosure, however, to avoid unnecessarily obscuring the variousembodiments of the disclosure. Further, those of ordinary skill in therelevant art will understand that they can practice other embodiments ofthe disclosure without one or more of the details described below.Finally, while various methods are described with reference to steps andsequences in the following disclosure, the description as such is forproviding a clear implementation of embodiments of the disclosure, andthe steps and sequences of steps should not be taken as required topractice this disclosure. Instead, the following is intended to providea detailed description of an example of the disclosure and should not betaken to be limiting of the disclosure itself. Rather, any number ofvariations may fall within the scope of the disclosure, which is definedby the claims that follow the description.

As will be appreciated by one skilled in the art, aspects of the presentdisclosure may be embodied as a system, method or computer programproduct. Accordingly, aspects of the present disclosure may take theform of an entirely hardware embodiment, an entirely software embodiment(including firmware, resident software, micro-code, etc.) or anembodiment combining software and hardware aspects that may allgenerally be referred to herein as a “circuit,” “module” or “system.”Furthermore, aspects of the present disclosure may take the form of acomputer program product embodied in one or more computer readablemedium(s) having computer readable program code embodied thereon.

Any combination of one or more computer readable medium(s) may beutilized. The computer readable medium may be a computer readable signalmedium or a computer readable storage medium. A computer readablestorage medium may be, for example, but not limited to, an electronic,magnetic, optical, electromagnetic, infrared, or semiconductor system,apparatus, or device, or any suitable combination of the foregoing. Morespecific examples (a non-exhaustive list) of the computer readablestorage medium would include the following: an electrical connectionhaving one or more wires, a portable computer diskette, a hard disk, arandom access memory (RAM), a read-only memory (ROM), an erasableprogrammable read-only memory (EPROM or Flash memory), an optical fiber,a portable compact disc read-only memory (CD-ROM), an optical storagedevice, a magnetic storage device, or any suitable combination of theforegoing. In the context of this document, a computer readable storagemedium may be any tangible medium that can contain, or store a programfor use by or in connection with an instruction execution system,apparatus, or device.

A computer readable signal medium may include a propagated data signalwith computer readable program code embodied therein, for example, inbaseband or as part of a carrier wave. Such a propagated signal may takeany of a variety of forms, including, but not limited to,electro-magnetic, optical, or any suitable combination thereof. Acomputer readable signal medium may be any computer readable medium thatis not a computer readable storage medium and that can communicate,propagate, or transport a program for use by or in connection with aninstruction execution system, apparatus, or device.

Program code embodied on a computer readable medium may be transmittedusing any appropriate medium, including but not limited to wireless,wireline, optical fiber cable, RF, etc., or any suitable combination ofthe foregoing.

Computer program code for carrying out operations for aspects of thepresent disclosure may be written in any combination of one or moreprogramming languages, including an object oriented programming languagesuch as Java, Smalltalk, C++ or the like and conventional proceduralprogramming languages, such as the “C” programming language or similarprogramming languages. The program code may execute entirely on theuser's computer, partly on the user's computer, as a stand-alonesoftware package, partly on the user's computer and partly on a remotecomputer or entirely on the remote computer or server. In the latterscenario, the remote computer may be connected to the user's computerthrough any type of network, including a local area network (LAN) or awide area network (WAN), or the connection may be made to an externalcomputer (for example, through the Internet using an Internet ServiceProvider).

Aspects of the present disclosure are described below with reference toflowchart illustrations and/or block diagrams of methods, apparatus(systems) and computer program products according to embodiments of thedisclosure. It will be understood that each block of the flowchartillustrations and/or block diagrams, and combinations of blocks in theflowchart illustrations and/or block diagrams, can be implemented bycomputer program instructions. These computer program instructions maybe provided to a processor of a general purpose computer, specialpurpose computer, or other programmable data processing apparatus toproduce a machine, such that the instructions, which execute via theprocessor of the computer or other programmable data processingapparatus, create means for implementing the functions/acts specified inthe flowchart and/or block diagram block or blocks. These computerprogram instructions may also be stored in a computer readable mediumthat can direct a computer, other programmable data processingapparatus, or other devices to function in a particular manner, suchthat the instructions stored in the computer readable medium produce anarticle of manufacture including instructions which implement thefunction/act specified in the flowchart and/or block diagram block orblocks.

The computer program instructions may also be loaded onto a computer,other programmable data processing apparatus, or other devices to causea series of operational steps to be performed on the computer, otherprogrammable apparatus or other devices to produce a computerimplemented process such that the instructions which execute on thecomputer or other programmable apparatus provide processes forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks.

The following detailed description will generally follow the summary ofthe disclosure, as set forth above, further explaining and expanding thedefinitions of the various aspects and embodiments of the disclosure asnecessary. To this end, this detailed description first sets forth acomputing environment in FIG. 1 that is suitable to implement thesoftware and/or hardware techniques associated with the disclosure. Anetworked environment is illustrated in FIG. 2 as an extension of thebasic computing environment, to emphasize that modern computingtechniques can be performed across multiple discrete devices.

FIG. 1 illustrates information handling system 100, which is asimplified example of a computer system capable of performing thecomputing operations described herein. Information handling system 100includes one or more processors 110 coupled to processor interface bus112. Processor interface bus 112 connects processors 110 to Northbridge115, which is also known as the Memory Controller Hub (MCH). Northbridge115 connects to system memory 120 and provides a means for processor(s)110 to access the system memory. Set of instructions 113 are stored insystem memory 120 for execution by the one or more processors 110.Graphics controller 125 also connects to Northbridge 115. In oneembodiment, PCI Express bus 118 connects Northbridge 115 to graphicscontroller 125. Graphics controller 125 connects to display device 130,such as a computer monitor.

Northbridge 115 and Southbridge 135 connect to each other using bus 119.In one embodiment, the bus is a Direct Media Interface (DMI) bus thattransfers data at high speeds in each direction between Northbridge 115and Southbridge 135. In another embodiment, a Peripheral ComponentInterconnect (PCI) bus connects the Northbridge and the Southbridge.Southbridge 135, also known as the I/O Controller Hub (ICH) is a chipthat generally implements capabilities that operate at slower speedsthan the capabilities provided by the Northbridge. Southbridge 135typically provides various busses used to connect various components.These busses include, for example, PCI and PCI Express busses, an ISAbus, a System Management Bus (SMBus or SMB), and/or a Low Pin Count(LPC) bus. The LPC bus often connects low-bandwidth devices, such asboot ROM 196 and “legacy” I/O devices (using a “super I/O” chip). The“legacy” I/O devices (198) can include, for example, serial and parallelports, keyboard, mouse, and/or a floppy disk controller. The LPC busalso connects Southbridge 135 to Trusted Platform Module (TPM) 195.Other components often included in Southbridge 135 include a DirectMemory Access (DMA) controller, a Programmable Interrupt Controller(PIC), and a storage device controller, which connects Southbridge 135to nonvolatile storage device 185, such as a hard disk drive, using bus184.

ExpressCard 155 is a slot that connects hot-pluggable devices to theinformation handling system. ExpressCard 155 supports both PCI Expressand USB connectivity as it connects to Southbridge 135 using both theUniversal Serial Bus (USB) the PCI Express bus. Southbridge 135 includesUSB Controller 140 that provides USB connectivity to devices thatconnect to the USB. These devices include webcam (camera) 150, infrared(IR) receiver 148, keyboard and trackpad 144, and Bluetooth device 146,which provides for wireless personal area networks (PANs). USBController 140 also provides USB connectivity to other miscellaneous USBconnected devices 142, such as a mouse, removable nonvolatile storagedevice 145, modems, network cards, ISDN connectors, fax, printers, USBhubs, and many other types of USB connected devices. While removablenonvolatile storage device 145 is shown as a USB-connected device,removable nonvolatile storage device 145 could be connected using adifferent interface, such as a Firewire interface, etcetera.

Wireless Local Area Network (LAN) device 175 connects to Southbridge 135via the PCI or PCI Express bus 172. LAN device 175 typically implementsone of the IEEE 802.11 standards of over-the-air modulation techniquesthat all use the same protocol to wireless communicate betweeninformation handling system 100 and another computer system or device.Optical storage device 190 connects to Southbridge 135 using Serial ATA(SATA) bus 188. Serial ATA adapters and devices communicate over ahigh-speed serial link. The Serial ATA bus also connects Southbridge 135to other forms of storage devices, such as hard disk drives. Audiocircuitry 160, such as a sound card, connects to Southbridge 135 via bus158. Audio circuitry 160 also provides functionality such as audioline-in and optical digital audio in port 162, optical digital outputand headphone jack 164, internal speakers 166, and internal microphone168. Ethernet controller 170 connects to Southbridge 135 using a bus,such as the PCI or PCI Express bus. Ethernet controller 170 connectsinformation handling system 100 to a computer network, such as a LocalArea Network (LAN), the Internet, and other public and private computernetworks.

While FIG. 1 shows one information handling system, an informationhandling system may take many forms. For example, an informationhandling system may take the form of a desktop, server, portable,laptop, notebook, or other form factor computer or data processingsystem. In addition, an information handling system may take other formfactors such as a personal digital assistant (PDA), a gaming device, ATMmachine, a portable telephone device, a communication device or otherdevices that include a processor and memory.

The Trusted Platform Module (TPM 195) shown in FIG. 1 and describedherein to provide security functions is but one example of a hardwaresecurity module (HSM). Therefore, the TPM described and claimed hereinincludes any type of HSM including, but not limited to, hardwaresecurity devices that conform to the Trusted Computing Groups (TCG)standard, and entitled “Trusted Platform Module (TPM) SpecificationVersion 1.2.” The TPM is a hardware security subsystem that may beincorporated into any number of information handling systems, such asthose outlined in FIG. 2.

FIG. 2 provides an extension example of the information handling systemenvironment shown in FIG. 1 to illustrate that the methods describedherein can be performed on a wide variety of information handlingsystems that operate in a networked environment. Types of informationhandling systems range from small handheld devices, such as handheldcomputer/mobile telephone 210 to large mainframe systems, such asmainframe computer 270. Examples of handheld computer 210 includepersonal digital assistants (PDAs), personal entertainment devices, suchas MP3 players, portable televisions, and compact disc players. Otherexamples of information handling systems include pen, or tablet,computer 220, laptop, or notebook, computer 230, workstation 240,personal computer system 250, and server 260. Other types of informationhandling systems that are not individually shown in FIG. 2 arerepresented by information handling system 280. As shown, the variousinformation handling systems can be networked together using computernetwork 200. Types of computer network that can be used to interconnectthe various information handling systems include Local Area Networks(LANs), Wireless Local Area Networks (WLANs), the Internet, the PublicSwitched Telephone Network (PSTN), other wireless networks, and anyother network topology that can be used to interconnect the informationhandling systems. Many of the information handling systems includenonvolatile data stores, such as hard drives and/or nonvolatile memory.Some of the information handling systems shown in FIG. 2 depictsseparate nonvolatile data stores (server 260 utilizes nonvolatile datastore 265, mainframe computer 270 utilizes nonvolatile data store 275,and information handling system 280 utilizes nonvolatile data store285). The nonvolatile data store can be a component that is external tothe various information handling systems or can be internal to one ofthe information handling systems. In addition, removable nonvolatilestorage device 145 can be shared among two or more information handlingsystems using various techniques, such as connecting the removablenonvolatile storage device 145 to a USB port or other connector of theinformation handling systems.

FIG. 3 is a flow diagram showing the steps taken to generate shape slackinformation and lithography tolerance bands. Three types of informationare extracted from hardware design layout 300. In the example shown,circuit sensitivity information is extracted using the process on theleft hand side, lithography sensitivity is extracted using the processin the middle, and power and performance specifications are extractedalong the right hand side.

In the process shown on the left side that extracts circuit sensitivity,at step 305, the first shape is selected from hardware design layout300. At step 310, the electrical characteristics are extracted from theselected shape At step 315, an electrical analysis (e.g., analysis ofpower and performance) is performed on the selected shape. Steps 310 and315 may be performed by using a standard circuit simulator to extractcircuit parameters at different configurations of the shape in question.The circuit sensitivity data derived from the electrical analysis arestored in circuit sensitivity data store 340. A determination is made asto whether there are more shapes in the design that need to be extractedand analyzed (decision 320). While there are more shapes to analyze,decision 320 loops back to step 305 to select and process the nextshape. This looping continues until there are no further shapes toanalyze, at which point decision 320 branches to “no” branch 330whereupon circuit sensitivity extraction and analysis ends at 335.

Lithography sensitivity process is extracted using the process shown inthe middle of FIG. 3. Here, at step 350, a lithography simulator is usedto process an emulation of the hardware design layout. The lithographysimulator uses models of the manufacturing process to generate theexpected shape on the wafer from the given target shape. Results of thesimulation point to the degree of difficulty in printing a given shape.This results in lithography sensitivity data that is stored in datastore 360. One possible metric for comparing lithography sensitivity isto compute the area of the process variability bands (PV Bands) for agiven shape. The band comprises of wafer contours at different processconditions and is indicative of how the feature will behave undervariability in the manufacturing process. A shape more difficult toprint will have wider PV Bands and a shape that is more easily printedwill have narrower PV Bands.

Power and performance specifications are extracted on the right side ofFIG. 3. As shown, power and performance specifications data store 370 isused to store the power and performance specifications that pertain tohardware design layout 300.

At step 375, shape tolerance analysis and optimization is performedusing circuit sensitivity data 340, lithography sensitivity 360, andpower and performance specifications 370 as inputs. Step 340 isexplained in greater detail in FIG. 4, while step 375 is explained ingreater detail in FIGS. 5 through 7. The result of step 375 aretolerance bands for each shape which are stored in tolerance bands datastore 380. These tolerance bands are then used by mask generator 390 togenerate the photolithographic mask. These tolerance bands provide arange of layouts that can provide electrical performance that are eachwithin tolerance. In essence, tolerance bands are designer-approvedtolerances for the lithography that aid manufacturing of the masks byallowing greater lithography flexibility without impacting theperformance of the hardware design.

FIG. 4 is a flowchart showing the steps taken to pre-characterizelibrary cells that are stored in a shape library. Processing commencesat 400 whereupon, at step 410, the first shape is selected from shapelibrary 430. In this example, shapes are the transistors representing bypolysilicon overlapping active area. A determination is made as towhether there are more input slews to process (decision 450). If thereare more input slews to process for the selected shape, then decision450 branches to “yes” branch 452 which loops back to select the nextinput slew for the selected shape. This looping continues until allinput slews for the selected shape have been selected and processed, atwhich time decision 450 branches to “no” branch 485.Shape library 430 isa data store that is used to store data pertaining to shapes used inhardware designs. As the name of the flowchart indicates, the processingperformed in FIG. 3 can be performed before any hardware designs need tobe analyzed so that the delay and slew data pertaining to the shapeswill be available when hardware designs are ready for analysis. At step420, the first input slew is selected for the selected shape. Input slewis the time taken for the signal at the input of a gate to change fromits initial value to its final value and is representative of the slopeor how slow/fast the signal changes. A faster changing signal willresult in lower delay and a slower changing signal will result in afaster delay. At step 425, a linear delay model is built for theselected input slew. The mathematical formula relates the change indelay at the output of the gate to the change in the shape dimension(which is gate length in this case) using a linear function. The delaydata resulting from this formula is stored in shape library 430. At step440 the linear output slew model is built. Output slew is the slew orslope at the output of a gate as opposed to the input of a gate. Adetermination is made as to whether there are more input slews toprocess (decision 450). If there are more input slews to process for theselected shape, then decision 450 branches to “yes” branch 452 whichloops back to select the next input slew for the selected shape. Thislooping continues until all input slews for the selected shape have beenselected and processed, at which time decision 450 branches to “no”branch 458.

At step 460, the first output load is selected for the selected shape.Output slew is the slope of the signal at the output of the gate,representing how fast or slow it changes. Output load is the capacitanceon the output pin of the gate. The higher the capacitance, the slowerthe signal will change.] At step 470, a linear model is built for theselected output slew. Once again, the delay model relates the outputdelay of the cell to the change in shape dimension (in this case, gatelength) using a linear approximation. The delay data resulting from thisformula is stored in shape library 430. At step 475, the linear slewmodel is built for the selected output slew. A determination is made asto whether there are more output slews to process (decision 480). Ifthere are more output slews to process for the selected shape, thendecision 480 branches to “yes” branch 485 which loops back to select thenext output slew for the selected shape. This looping continues untilall output slews for the selected shape have been selected andprocessed, at which time decision 480 branches to “no” branch 490 whichloops back to step 410 which selects the next shape from shape library430 and builds the delay and slew models as described above. Thislooping continues until all of the shapes in shape library 430 have beenprocessed, at which the processing shown in FIG. 4 ends. As new shapesare added to shape library 430 (e.g., because of a new hardware design,etc.), these new shapes are characterized using the steps shown in FIG.4 so that the delay and slew data is available in the shape library.

FIG. 5 is a flowchart showing the steps taken to convert electricalslack in the hardware design to physical shape slack. Processingcommences at 500 whereupon, during a first phase, predefined process 510is performed to determine the electrical slack distribution (see FIG. 6and corresponding text for processing details). Electrical slack is forthe design as a whole. FIG. 5 shows how to propagate this slack toshapes in the design in the form of shape slack. The delay rangeresulting from predefined process 510 is stored in delay range 520.Delay range represents the maximum and minimum values of delay withinwhich a gate can operate while still meeting design requirements.

During a second phase, predefined process 530 is performed to convertthe delay slack into shape slack (see FIG. 7 and corresponding text forprocessing details). Inputs to predefined process 530 include shapeweightings 525 which is provided by lithography processes as well asdelay range data 520 resulting from phase 1. The data for 520 isobtained by the procedure described for 360 previously shown in FIG. 3.The result of predefined process 530 are tolerances data 540 whichindicate the inner and outer bounds of a shape (e.g., shape 550). Asshown in the example, shape 550 has inner bound (tolerance) 551 which isa smaller footprint than outer bound (tolerance) 552. So long as theshape is generated within these inner and outer bounds it will beacceptable to the hardware design. Mask generator 570 generates mask 580taking the hardware design layout 560 as input as well as tolerancesdata 540. The mask generator has flexibility to generate the mask forthe hardware design layout using the tolerances (inner/outer tolerances)provided for each shape. Some shapes might have tighter, or moreprecise, tolerances than other shapes in the design.

FIG. 6 is a flowchart of a first phase in converting the electricalslack in the design to physical shape slack by analyzing the electricalslack distribution in the design. Processing commences at 600 whereupon,at step 620 all of the gates in the hardware design are selected at thesame time. The hardware design representation is netlist data store 610.All of the gates in the netlist are selected simultaneously because theway in which the slack gets divided amongst the gates depends on howthey are interconnected. For example, if there are five gates connectedto each other on a path with some slack, the slack should be dividedequally among the five gates as opposed to giving all the slack to justone of the gates. Each gate selected from hardware design 610 isprocessed by steps 630 to 690 in parallel (essentially, simultaneouslywith the other gates). At step 630, the delay of each gate is computedas a function of the input slew and output load pertaining to each ofthe gates. This is a well-known computation that is done by all timingtools. It involves the use of lookup tables. At step 640, slackvariables are established for each gate (S_(i)) and assigned to eachgate's late mode (which is constrained by setup time). The late mode ofa gate determines the latest time at which the output of a gate willchange. Early mode determines the opposite, i.e. what is the earliest atwhich the output of the gate will change. The latest arriving time isconstrained by the setup time at a latch/flip-flop into which the outputof the gate will be stored. Early mode is constrained by the hold timeof the same latch/flip-flop. At step 650, slack variables areestablished for each gate (H_(i)) and assigned to each gate's early modewhich is constrained by hold time. At step 660, the allowable delayrange of each gate is computed to be in the range of the sum of thedelay and the hold time to the sum of the delay and the late mode (inthe range of (D_(i)+H_(i)) to (D_(i)+S_(i))). So long as the delay ofeach of the gates is between this range (established for each of thegates) the timing constraints of the hardware design will not beviolated. At step 670, the arrival time at each gate's output gate(a_(i)) is computed.

The delays, setup times, hold times, allowable ranges, and arrival timesare fed into the equation shown in step 690 along with the list ofprimary input nodes (675) and the list of primary output nodes (680).Step 690 takes as input, the delays of each gate along with theirconnectivity as well as the design constraints in terms of setup timesand hold times at each flop/latch. It then uses the optimizationformulation outlined to generate the delay slack values (S_(i),H_(i))for each gate such that design constraints are satisfied. Theoptimization formulation for 690 may be solved as a linear program (LP)using a commercial LP solver.

FIG. 7 is a flowchart of a second phase in converting the electricalslack in the design to physical shape slack by converting the delayslack to shape slack. In FIG. 7, the delay ranges computed in FIG. 6 areconverted to allowable shape tolerances. Processing commences at 700whereupon, at step 705, the number of gates in hardware design 610 isidentified (set in the example to variable N). The current gate that isbeing processed is set to the first gate (initializing variable i to 1).At step 710, the first gate from netlist 610 is selected and each shapein the selected gate is assigned an identifier (1 to M with M being thenumber of shapes in the selected gate). At step 715, all of the shapes(1 to M) in the selected gate are selected for simultaneous (ornear-simultaneous) processing. At step 720, the drawn dimension of eachshape is assigned to the variable L (e.g., L₁ to L_(M)). At step 725, anouter bound of each shape is assigned to the variable O (e.g., O₁ toO_(M)). Likewise, at step 730, an inner bound of each shape is assignedto the variable I (e.g.,I₁ to I_(M)). When processing is completed, eachof the shapes will have a computed inner and outer bound value assignedthat specifies a physical range tolerance. So, for example, the firstshape in the netlist will have a drawn dimension of L₁, an inner bounddimension of I₁, and an outer bound dimension of O₁. When the maskgenerator is generating the mask for this first shape, the shape of themask can be anywhere between these bounds and still create an acceptablemask for the hardware design.

At step 740, the total shape slack (range) is maximized using theequations shown in 750 and is subject to timing constraints determinedin Phase 1 (see FIG. 6 and corresponding text for details regardingcomputation of timing constraints). Each gate has a delay range that wascomputed in Phase 1. In addition, each of the shapes can have a weightapplied. In one embodiment, the weight can be driven by lithographyprocesses. Box 750 describes the optimization formulation for generatingan inner (I_(j)) and outer (O_(j)) tolerance on each shape in a gategiven the range of delay values (D_(i)+H_(i),D_(i)+S_(i)) that the gatecan take. The weights (wj) are obtained from the computations performedfor litho sensitivity in 360. The result of step 740 are tolerancesstored in tolerances data store 755 that include inner and outer bounds(I_(j) and O_(j)) for each shape in the gate. These tolerances are usedby the mask generator to create shapes (e.g. shape 550) within thisphysical range tolerance.

A determination is made as to whether there are more gates in thehardware design to process (decision 760). If there are more gates toprocess, decision 760 branches to “yes” branch 765 whereupon, at step770, the gate variable (i) is incremented to represent the next gate inthe hardware design. Processing then loops to the beginning of theprocess (step 710) to select the next gate in the design, select all ofthe shapes in the next gate, and process the selected shapes asdescribed above. This looping continues until there are no more gates inhardware design 610 to process, at which point decision 760 branches to“no” branch 775 and processing ends at 795.

The flowchart and block diagrams in the FIGures illustrate thearchitecture, functionality, and operation of possible implementationsof systems, methods and computer program products according to variousembodiments of the present disclosure. In this regard, each block in theflowchart or block diagrams may represent a module, segment, or portionof code, which comprises one or more executable instructions forimplementing the specified logical function(s). It should also be notedthat, in some alternative implementations, the functions noted in theblock may occur out of the order noted in the FIGures. For example, twoblocks shown in succession may, in fact, be executed substantiallyconcurrently, or the blocks may sometimes be executed in the reverseorder, depending upon the functionality involved. It will also be notedthat each block of the block diagrams and/or flowchart illustration, andcombinations of blocks in the block diagrams and/or flowchartillustration, can be implemented by special purpose hardware-basedsystems that perform the specified functions or acts, or combinations ofspecial purpose hardware and computer instructions.

While particular embodiments of the present disclosure have been shownand described, it will be obvious to those skilled in the art that,based upon the teachings herein, that changes and modifications may bemade without departing from this disclosure and its broader aspects.Therefore, the appended claims are to encompass within their scope allsuch changes and modifications as are within the true spirit and scopeof this disclosure. Furthermore, it is to be understood that thedisclosure is solely defined by the appended claims. It will beunderstood by those with skill in the art that if a specific number ofan introduced claim element is intended, such intent will be explicitlyrecited in the claim, and in the absence of such recitation no suchlimitation is present. For non-limiting example, as an aid tounderstanding, the following appended claims contain usage of theintroductory phrases “at least one” and “one or more” to introduce claimelements. However, the use of such phrases should not be construed toimply that the introduction of a claim element by the indefinitearticles “a” or “an” limits any particular claim containing suchintroduced claim element to disclosures containing only one suchelement, even when the same claim includes the introductory phrases “oneor more” or “at least one” and indefinite articles such as “a” or “an”;the same holds true for the use in the claims of definite articles.

1. A machine-implemented method comprising: computing, by a processor, aplurality of electrical delay ranges corresponding to a plurality ofshapes included in a hardware design layout; creating a plurality ofshape tolerances, wherein each shape tolerance of the plurality of shapetolerances are applied to one of the plurality of shapes, and whereineach shape tolerance of the plurality of shape tolerances is based on acorresponding computed electrical delay range in the plurality ofcomputed electrical delay ranges; and generating a lithography mask ofthe hardware design layout, wherein images of each of the shapes isincluded in the lithography mask within the shape tolerances thatcorrespond to each of the shapes.
 2. The machine implemented method ofclaim 1, wherein the computing of the plurality of electrical delayranges further comprises: selecting a plurality of gates included in anetlist corresponding to the hardware design layout, wherein each gateincludes one or more of the plurality of shapes; computing a delay ofeach gate as a function of an input slew and an output loadcorresponding to each gate; and computing the plurality of electricaldelay ranges corresponding to each of the gates as being between anearly value and a late value, wherein the early value is the computeddelay corresponding to each gate added to a hold time corresponding toeach gate, and wherein the late value is the computed delaycorresponding to each gate added to a setup time corresponding to eachgate.
 3. The machine implemented method of claim 2, further comprising:selecting a first gate of the plurality of gates; selecting all of theshapes included in the first gate; retrieving a drawn dimension of eachshape; and computing a minimum inner bound and a maximum outer boundcorresponding to each shape using the computed early and late values,wherein the shape tolerance corresponding to each shape include thecomputed minimum inner bound and maximum outer bound.
 4. The machineimplemented method of claim 3, further comprising: retrieving aweighting value corresponding to at least one of the shapes, wherein thecomputing of the minimum inner bound and maximum outer bound applies theweighting value to the computation.
 5. The machine implemented method ofclaim 3, further comprising: generating the lithography mask of thehardware design layout wherein a plurality of the shapes included in thelithography mask have different dimensions than the retrieved drawndimension of the shape.
 6. The machine implemented method of claim 2,wherein selection, computation of delay, and computation of theplurality of electrical delay ranges of each of the gates are performedin parallel.
 7. The machine implemented method of claim 1, furthercomprising: retrieving a list of primary input nodes and a list ofprimary output nodes for a plurality of gates included in a netlistcorresponding to the hardware design layout; and computing the pluralityof electrical delay ranges based upon the primary input nodes and theprimary output nodes corresponding to the plurality of gates.
 8. Acomputer readable storage medium having instructions stored thereonthat, when executed by an information handling system, cause theinformation handling system to perform actions that include: computing,by a processor, a plurality of electrical delay ranges corresponding toa plurality of shapes included in a hardware design layout; creating aplurality of shape tolerances, wherein each shape tolerance of theplurality of shape tolerances are applied to one of the plurality ofshapes, and wherein each shape tolerance of the plurality of shapetolerances is based on a corresponding computed electrical delay rangein the plurality of computed electrical delay ranges; and generating alithography mask of the hardware design layout, wherein images of eachof the shapes is included in the lithography mask within the shapetolerances that correspond to each of the shapes.
 9. The computerreadable storage medium of claim 8, wherein the computing of theplurality of electrical delay ranges further comprises additionalactions comprising: selecting a plurality of gates included in a netlistcorresponding to the hardware design layout, wherein each gate includesone or more of the plurality of shapes; computing a delay of each gateas a function of an input slew and an output load corresponding to eachgate; and computing the plurality of electrical delay rangescorresponding to each of the gates as being between an early value and alate value, wherein the early value is the computed delay correspondingto each gate added to a hold time corresponding to each gate, andwherein the late value is the computed delay corresponding to each gateadded to a setup time corresponding to each gate.
 10. The computerreadable storage medium of claim 9, wherein the instructions cause theinformation handling system to perform further actions comprising:selecting a first gate of the plurality of gates; selecting all of theshapes included in the first gate; retrieving a drawn dimension of eachshape; and computing a minimum inner bound and a maximum outer boundcorresponding to each shape using the computed early and late values,wherein the shape tolerance corresponding to each shape include thecomputed minimum inner bound and maximum outer bound.
 11. The computerreadable storage medium of claim 10, wherein the instructions cause theinformation handling system to perform further actions comprising:retrieving a weighting value corresponding to at least one of theshapes, wherein the computing of the minimum inner bound and maximumouter bound applies the weighting value to the computation.
 12. Thecomputer readable storage medium of claim 10, wherein the instructionscause the information handling system to perform further actionscomprising: generating the lithography mask of the hardware designlayout wherein a plurality of the shapes included in the lithographymask have different dimensions than the retrieved drawn dimension of theshape.
 13. The computer readable storage medium of claim 8, wherein theactions of selecting, computing a delay, and computing the plurality ofelectrical delay ranges of each of the gates are performed in parallel.14. The computer readable storage medium of claim 8, wherein theinstructions cause the information handling system to perform furtheractions comprising: retrieving a list of primary input nodes and a listof primary output nodes for a plurality of gates included in a netlistcorresponding to the hardware design layout; and computing the pluralityof electrical delay ranges based upon the primary input nodes and theprimary output nodes corresponding to the plurality of gates.
 15. Aninformation handling system comprising: one or more processors; a memoryaccessible by at least one of the processors; a nonvolatile storage areaaccessible by at least one of the processors; wherein the memory storesa set of instructions, which when executed by at least one of theprocessors, performs actions of: computing a plurality of electricaldelay ranges corresponding to a plurality of shapes included in ahardware design layout; creating a plurality of shape tolerances,wherein each shape tolerance of the plurality of shape tolerances areapplied to one of the plurality of shapes, and wherein each shapetolerance of the plurality of shape tolerances is based on acorresponding computed electrical delay range in the plurality ofcomputed electrical delay ranges; and generating a lithography mask ofthe hardware design layout, wherein images of each of the shapes isincluded in the lithography mask within the shape tolerances thatcorrespond to each of the shapes.
 16. The information handling system ofclaim 15, wherein the computing of the plurality of electrical delayranges causes the processor to perform further actions comprising:selecting a plurality of gates included in a netlist corresponding tothe hardware design layout, wherein each gate includes one or more ofthe plurality of shapes; computing a delay of each gate as a function ofan input slew and an output load corresponding to each gate; andcomputing the plurality of electrical delay ranges corresponding to eachof the gates as being between an early value and a late value, whereinthe early value is the computed delay corresponding to each gate addedto a hold time corresponding to each gate, and wherein the late value isthe computed delay corresponding to each gate added to a setup timecorresponding to each gate.
 17. The information handling system of claim16, wherein the information handling system performs further actionscomprising: selecting a first gate of the plurality of gates; selectingall of the shapes included in the first gate; retrieving a drawndimension of each shape; and computing a minimum inner bound and amaximum outer bound corresponding to each shape using the computed earlyand late values, wherein the shape tolerance corresponding to each shapeinclude the computed minimum inner bound and maximum outer bound. 18.The information handling system of claim 17, wherein the informationhandling system performs further actions comprising: retrieving aweighting value corresponding to at least one of the shapes, wherein thecomputing of the minimum inner bound and maximum outer bound applies theweighting value to the computation.
 19. The information handling systemof claim 17, wherein the information handling system performs furtheractions comprising: generating the lithography mask of the hardwaredesign layout wherein a plurality of the shapes included in thelithography mask have different dimensions than the retrieved drawndimension of the shape.
 20. The information handling system of claim 16,wherein the actions of selecting, computing a delay, and computing theplurality of electrical delay ranges of each of the gates are performedin parallel.